One of the emerging chip architectures/technologies for both integrated circuits (ICs) and microelectro-mechanical systems (MEMS) is 3D integration based on bonding together semiconductor devices with pre-fabricated components. For example, a flip chip is a method for interconnecting semiconductor devices by flipping over one of the devices so that its top side faces down, aligning the bond pads to match with the other device's bond pads, and bonding the devices together. Prior to the flipping, aligning, and bonding, vias and bond pads are patterned on pre-processed wafers and filled by a copper damascene process. Specifically, dielectric layers, for example low temperature inorganic dielectrics such as silicon dioxide (SiO2), silicon nitride (Si3N4), and/or silicon carbide (SiC) are formed on the wafer and etched to form vias. Then, copper is deposited in the vias by plating or chemical vapor deposition (CVD) of the copper. Since copper diffuses rapidly in dielectrics, a barrier material such as TiN is deposited as a liner before copper is deposited. Excess copper is then removed and the surface of the copper and dielectric layer is planarized by chemical-mechanical polishing (CMP). The preprocessed wafers are aligned and bonded together at or near room temperature using chemical or plasma activated fusion bonding processes compatible with back-end-of-the-line (BEOL) wafers. As the surfaces of the dielectric layers are physically bonded together, the planar copper layers come in contact and, after annealing, interconnects between the devices are formed through copper-to-copper bonds in the bond pads for both structural integrity and inter-wafer electrical interconnections.
As shown in FIGS. 1A and 1B, a Si device (either a wafer or die) 101 having a dielectric layer 103 and copper bond pads 105, when subjected to CMP often results in dishing 107 of the bond pads. When two planarized Si devices 101 are joined, aligned and bonded together, dishing leads to voids 109 in the copper interconnect. Since even a few nanometers of dishing below the dielectric surface can prevent successful joint formation, the dishing of the bond pads needs to be controlled or minimized. (In FIGS. 1A and 1B, the top and bottom dies only show the top pad in a BEOL stack for illustration convenience. There may be multiple metal/dielectric layers in the BEOL stack.)
A need therefore exists for methodology enabling fabrication of 3D integrated ICs and MEMS with controlled and/or reduced dishing at the bond pads.